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1/26 not for new design november 2004 this is information on a product still in production but not recommended for new designs. M48T254V 3.3v, 16 mbit (2mb x 8bit) timekeeper ? sram with phantom clock features summary 3.3v 10% integrated ultra low power sram, real time clock, power-fail control circuit, battery and crystal real time clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, days, date, months, and years. clock function is transparent to ram operation. precision power monitoring and power switching circuitry automatic write-protection when v cc is out-of-tolerance power-fail deselect voltage: ?v cc = 3.3v 10%; 2.8v v pfd 2.97v battery low (bl ) 10 years of data retention and clock operation in the absence of power snaphat housing (battery/crystal) is replaceable 100ns acc ess (read = write) figure 1. 168-ball pbga module figure 2. snaphat crystal/battery M48T254V 168-ball pbga module (za) snaphat (sh) crystal/battery
M48T254V 2/26 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. 168-ball pbga module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. snaphat crystal/battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. pbga connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 5. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. M48T254V pbga module solution (side/top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. memory read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. memory write cycle, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. memory write cycle, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 phantom clock operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 10.comparison register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 clock register information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 am-pm/12/24 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 oscillator bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 zero bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. rtc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11.phantom clock read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12.phantom clock write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 battery low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13.ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14.power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/26 M48T254V package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15.pbga-za ? 168-ball plastic ball grid array package outline . . . . . . . . . . . . . . . . . . . . 21 table 10. pbga-za ? 168-ball plastic ball grid array package mechanical data . . . . . . . . . . . . . 22 figure 16.sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline . . . . . . 23 table 11. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data. . . 23 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 table 13. snaphat battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
M48T254V 4/26 summary description the M48T254V timekeeper ? ram is a 2mbit x 8 non-volatile static ram and real time clock orga- nized as 2,097,152 words by 8 bits. the special bga package provides a fully integrated battery back-up memory and real time clock solution. in the event of power instability or absence, a self- contained battery maintains the timekeeping oper- ation and provides power for a cmos static ram. control circuitry monitors v cc and invokes write protection to prevent data corruption in the memo- ry and rtc. the clock keeps track of tenths/hundredths of sec- onds, seconds, minutes, hours, day, date, month, and year information. the last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. the clock operates in one of two formats: ? a 12-hour mode with an am/pm indicator; or ? a 24-hour mode the M48T254V is a 168-ball pbga module that in- tegrates the rtc, the battery, and sram in one package. figure 3. logic diagram table 1. signal names ai04217 v cc M48T254V v ss bl a0 ? a20 dq0 ? dq7 we oe ce a0 - a20 address inputs dq0 - dq7 data input/output ce chip enable we write enable inputs oe output enable bl battery low output (open drain) nc no connect v cc supply voltage v ss ground
5/26 M48T254V figure 4. pbga connections (top view) note: this diagram is top view perspective (view through package). ai04216 1 2 3 4 5 6 7 8 9 v cc v cc a7 a6 a5 gnd a4 a3 a2 a1 21 22 23 24 25 26 27 28 29 40 41 39 38 37 36 35 34 33 32 31 30 10 11 12 13 14 15 16 17 18 19 20 a0 dq0 dq1 dq2 dq3 gnd dq4 dq5 dq6 dq7 v cc v cc a8 a9 a10 a11 gnd a12 a13 a14 a15 a16 a17 a18 a19 gnd a20 M48T254V bl ce oe we
M48T254V 6/26 figure 5. hardware hookup m68z512w rst bl v ss e e e e m40z300w v cc v cc v cc e ths (not bonded) to battery monitor circuitry .1f .1f v cc oe cei ce oe we we m68z512w m68z512w m68z512w w we g oe we oe g w g w g w ceo v out v out v out rst bl e3 con e4 con v ss m40z300w v cc v cc v cc ths e1 con e2 con a0-a18 a0-a18 a0-a18 a0-a18 dq0-dq7 dq0-dq7 dq0-dq7 dq0-dq7 3.3v 3.3v 3.3v 8 8 8 8 19 19 19 19 3.3v m41t315v e e ai04215 d q dq0 a b a19 a20
7/26 M48T254V figure 6. M48T254V pbga module solution (side/top) ai04214b
M48T254V 8/26 operation modes read a read cycle executes whenever write enable (we ) is high and chip enable (ce ) is low (see fig- ure 7., page 9 ). the distinct address defined by the 21 address inputs (a0-a20) specifies which of the 2m bytes of data is to be accessed. valid data will be accessed by the eight data output drivers within the specified access time (t acc ) after the last address input signal is stable, the ce and oe access times, and their respective parameters are satisfied. when ce t acc and oe t acc are not sat- isfied, then data access times must be measured from the more recent ce and oe signals, with the limiting parameter being t co (for ce ) or t oe (for oe ) instead of address access. write write mode occurs whenever ce and we sig- nals are low (after address inputs are stable, see figure 8., page 9 and figure 9., page 10 ). the most recent falling edge of ce and we will deter- mine when the write cycl e begins (the earlier, rising edge of ce or we determines cycle termina- tion). all address inputs must be kept stable throughout the write cycle. we must be high (in- active) for a minimum recovery time (t wr ) before a subsequent cycle is initiated. the oe control sig- nal should be kept high (inactive) during the write cycles to avoid bus contention. if ce and oe are low (active), we will disable the outputs for output data write time (t odw ) from its falling edge. data retention mode data can be read or written only when v cc is greater than v pfd . when v cc is below v pfd (the point at which write protection occurs), the clock registers and the sram are blocked from any ac- cess. when v cc falls below the battery switch over threshold (v so ), the device is switched from v cc to battery backup (v bat ). rtc operation and sram data are maintained via battery backup un- til power is stable. all control, data, and address signals must be powered down when v cc is pow- ered down. the lithium power source is designed to provide power for rtc activity as well as rtc and ram data retention when v cc is absent or unstable. the capability of this source is sufficient to power the device continuously for the life of the equip- ment into which it has been installed. for specifi- cation purposes, life expectancy is ten (10) years at 25c with the internal oscillator r unning without v cc . the actual life expec tancy will be much long- er if no battery energy is used (e.g., when v cc is present). table 2. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage 1. see table 9., page 20 for details. mode v cc ce oe we dq7-dq0 power deselect 3.0v to 3.6v v ih x x high-z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high-z active deselect v so to v pfd (min) (1) x x x high-z cmos standby deselect v so (1) x x x high-z battery back-up
9/26 M48T254V figure 7. memory read cycle note: we is high for a read cycle. figure 8. memory write cycle, write enable controlled note: 1. oe = v ih or v il . if oe = v ih during a write cycle, the output buffers remain in a high impedance state. 2. if the ce low transition occurs simultaneously with or later than the we low transition in we controlled write, the output buffers remain in a high impedance state during this period. 3. if the ce high transition occurs simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. dq0 - dq7 addresses oe ce data output valid tod todo toe trc tco tacc tcoe tcoe toh ai04230 ai05655 dq0?dq7 addresses we ce data i n stable tah1 toew tdh1 tds twc todw twp taw high impedance
M48T254V 10/26 figure 9. memory write cycle, chip enable controlled note: 1. oe = v ih or v il . if oe = v ih during a write cycle, the output buffers remain in a high impedance state. 2. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. ai05656 dq0?dq7 addresses we ce data i n stable tah2 toew twc todw tds tdh2 tcoe twp taw
11/26 M48T254V table 3. ac electrical characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 3.0 to 3.6v (except where noted). 2. these parameters are sampled with a 5 pf load are not 100% tested. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t wr is a function of the latter occurring edge of we or ce . symbol parameter (1) min max unit t avav t rc read cycle time 100 ns t avqv t acc access time 100 ns t elqv t co chip enable low to output valid 100 ns t glqv t oe output enable low to output valid 55 ns t elqx t coe (2) chip enable or output enable low to output transition 5 ns t axqx t oh output hold from address change 5 ns t ehqz t od (2) chip enable high to output hi-z 35 ns t ghqz t odo (2) output enable high to output hi-z 35 ns t wlqz t odw (2) output hi-z from we 35 ns t avav t wc write cycle time 100 ns t wlwh t eleh t wp (3) we , ce pulse width 70 ns t av el t aw address setup time 0 ns t whax t ah1 address hold time from we 5ns t ehax t ah2 address hold time from ce 25 ns t whqx t oew (2) output active from we 5ns t dv eh t dvwh t ds data setup time 40 ns t whdx t dh1 data hold time from we 0ns t ehdx t dh2 data hold time from ce 20 ns t rr read recovery (clock access only) 20 ns t wr (4) write recovery (clock access only) 20 ns
M48T254V 12/26 phantom clock operation communication with the phantom clock is estab- lished by pattern recognition of a serial bit-stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on dq0. all accesses which occur prior to recognition of the 64-bit pattern are directed to memory. after recognition is established, the next 64 read or write cycles either extract or update data in the clock while disabling the memory. data transfer to and from the timekeeping function is accomplished with a serial bit-stream under con- trol of chip enable (ce ), output enable (oe ), and write enable (we ). initially, a read cycle using the ce and oe control of the clock starts the pat- tern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register (see figure 10., page 13 ). next, 64 consecutive write cycles are executed using the ce and we control of the device. these 64 write cycles are used only to gain access to the clock. therefore, any address to the memory is acceptable. however, the write cycles gener- ated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requirement is to set aside just one address location in ram as a phan- tom clock scratch pad. when the first write cycle is executed, it is com- pared to bit 1 of the 64-bit comparison register. if a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. if a match is not found, the pointer does not ad- vance and all subsequent write cycles are ig- nored. if a read cycle occurs at any time during pattern recognition, the present sequence is abort- ed and the comparison register pointer is reset. pattern recognition continues for a total of 64 write cycles as described above until all of the bits in the comparison register have been matched. with a correct match for 64-bits, the phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. the next 64 cycles will cause the phantom clock to ei- ther receive or transmit data on dq0, depending on the level of the oe pin or the we pin. cycles to other locations outside the memory block can be interleaved with ce cycles without interrupting the pattern recognition sequence or data transfer se- quence to the phantom clock.
13/26 M48T254V figure 10. comparison register definition note: the odds of this pattern being accidentally duplicated and sending aberrant entries to the rtc is less than 1 in 10 19 . this pattern is sent to the clock lsb to msb. 7 65 432 1 0 byte 0 byte 1 by te 2 byte 3 by te 4 by te 5 byte 6 by te 7 hex value 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 c5 3a a3 5c c5 3a a3 5c ai04262
M48T254V 14/26 clock register information clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one (1) bit at a time after the 64-bit pattern recognition sequence has been completed. when updating the clock registers, each must be handled in groups of 8 bits. writing and reading individual bits within a register could produce erroneous results. these read/write registers are defined in the clock register map (see table 4. ). data contained in the clock registers is in binary coded decimal format (bcd). reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. am-pm/12/24 mode bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. when it is high, the 12- hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with the logic high being ?pm.? in the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). oscillator bit bit 5 controls the oscillator. when set to logic '0,' the oscillator turns on and the rtc/calendar be- gins to increment. zero bits registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' when writ- ing to these locations, either a logic '1' or '0' is ac- ceptable. table 4. rtc register map keys: a/p = am/pm bit 12/24 = 12 or 24-hour mode bit osc = oscillator bit rst = reset bit 0 = must be set to '0' 1 = must be set to '1' function/range bcd format register d7 d6 d5 d4 d3 d2 d1 d0 0 0.1 seconds 0.01 seconds seconds 00-99 1 0 10 seconds seconds seconds 00-59 2 0 10 minutes minutes minutes 00-59 3 12/24 0 10/ a/p hrs hours (24 hour format) hours 01-12/ 00-23 400osc 1 0 day of the week day 01-7 5 0 0 10 date date: day of the month date 01-31 6 0 0 0 10m month month 01-12 7 10 years year year 00-99
15/26 M48T254V figure 11. phantom clock read cycle figure 12. phantom clock write cycle data output valid we ce oe q tcw tco trc tow tcoe todo trr tod toe toee ai04259 data input stable oe d ce twp twc tcw tdh1 twr tah2 we tdh2 tds ai05658
M48T254V 16/26 battery low the M48T254V automatically performs battery voltage monitoring upon power-up, and at factory- programmed time intervals of at least 24 hours. the battery low (bl ) signal will be asserted if the battery voltage is found to be less than approxi- mately 2.5v. the bl signal will remain asserted until completion of battery replacement and sub- sequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up se- quence, this indicates that one of the batteries is below 2.5v and may not be able to maintain data integrity in the sram. data should be considered suspect, and verified as correct. all three snaphat ? tops should be replaced. if a battery low indication is generated during the 24-hour interval check, this indicates that one of the batteries is near end of life. however, data is not compromised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the batteries should be replaced. the snaphat top should be replaced with valid v cc applied to the device. the M48T254V only monitors the batteries when a nominal v cc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. the bl signal is an open drain output and an appropriate pull-up resistor should be cho- sen to control the rise time. note: the bl signal is available only for the exter- nal sram, not for the real-time clock.
17/26 M48T254V maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 5. absolute maximum ratings caution! negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. symbol parameter value unit t a operating temperature 0 to 70 c t stg storage temperature (v cc , oscillator off) ?40 to 85 c t sld lead solder temperature for 10 seconds 260 c v cc supply voltage (on any pin relative to ground) ?0.3 to +4.6 v v io input or output voltages ?0.3 to v cc + 0.3 v i o output current 20 ma p d power dissipation 1 w
M48T254V 18/26 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 6. dc and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 13. ac testing load circuit table 7. capacitance note: 1. effective capacitance measured with power supply at 3v. sampled only; not 100% tested. 2. at 25c, f = 1mhz. 3. outputs were deselected. parameter m41t254v v cc supply voltage 3.0 to 3.6v ambient operating temperature 0 to 70c load capacitance (c l ) 50pf input rise and fall times 5ns input pulse voltages 0 to 3v input and output timing ref. voltages 1.5v c l = 50 pf device under test 645 ? ai04644 1.75v symbol parameter (1,2) min max unit c in input capacitance (a0-a18, oe , we , ce )40pf input capacitance (a19-a20) 10 pf c out output capacitance (bl )20pf c io (3) input / output capacitance 40 pf
19/26 M48T254V table 8. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 3.0 to 3.6v (except where noted). 2. all voltages are referenced to ground. 3. for bl pin (open drain). sym parameter test condition (1) M48T254V unit min typ max i li input leakage current 0v v in v cc 4 a i lo output leakage current 0v v out v cc 4 a i cc1 supply current 50 ma i cc2 supply current (ttl standby) ce = v ih 57ma i cc3 v cc power supply current ce = v cci ? 0.2 23ma v il (2) input low voltage ?0.3 0.6 v v ih (2) input high voltage 2.2 v cc + 0.3 v v ol (3) output low voltage (open drain) i ol = 10ma 0.4 v output low voltage i ol = 2.0ma 0.4 v v oh output high voltage i oh = ?1.0ma 2.4 v v pfd (2) power fail deselect 2.80 2.97 v v so (2) battery back-up switchover 2.5 v
M48T254V 20/26 figure 14. power down/up mode ac waveforms table 9. power down/up trip points dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 3.0 to 3.6v (except where noted). 2. at 25c, v cc = 0v; the expected t dr is defined as cumulative time in the absence of v cc with the clock oscillator running. 3. (requires use of three m4t32-br12sh snaphat ? tops.) symbol parameter (1) min max unit t rec v pfd (max) to ce low 40 120 ms t f v pfd (max) to v pfd (min) v cc fall time 300 s t fb v pfd (min) to v so v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 0 s t pd ce high to power-fail 0 s t dr (2) expected data retention time 10 years tdr tf trec tr tpd tfb v so v cc ce v pfd (max) v pfd (min) ai05657 don't care
21/26 M48T254V package mechanical information figure 15. pbga-za ? 168-ball plastic ball grid array package outline note: drawing is not to scale. pbga-z02 top view d ge je gd hd he e 45? b a bottom view d1 e e1 d e fd b e e fe pin 1 corner 0.20 (4x) detail a detail a solder ball (typ) c s c a b fff eee b s s s side view (sh x 1) b1 side view (sh x 2) b a2 a1 a a3 ddd c
M48T254V 22/26 table 10. pbga-za ? 168-ball plastic ball grid array package mechanical data symb mm inches typ min max typ min max a 2.94 2.74 3.14 0.116 0.108 0.124 a1 0.89 0.69 1.09 0.035 0.027 0.043 a2 11.53 11.18 11.88 0.454 0.440 0.468 a3 7.24 8.00 0.285 0.315 b 38.54 38.34 38.74 1.517 1.509 1.525 b1 21.21 21.84 0.835 0.860 b 0.76 0.71 0.81 0.030 0.028 0.032 d 42.50 42.30 42.70 1.673 1.665 1.681 d1 27.94 1.100 e 42.50 42.30 42.70 1.673 1.665 1.681 e1 22.86 0.900 e 1.27 0.050 fd 7.28 7.18 7.38 0.287 0.283 0.291 fe 9.82 9.72 9.92 0.387 0.383 0.391 gd 1.75 1.55 1.95 0.069 0.061 0.077 ge 1.50 1.30 1.70 0.059 0.051 0.067 hd 1.98 1.78 2.18 0.078 0.070 0.086 he 0.51 0.31 0.71 0.020 0.012 0.028 je 1.50 1.30 1.70 0.059 0.051 0.067 n 168 168 tolerance tolerance ddd 0.15 0.006 eee 0.30 0.012 fff 0.15 0.006
23/26 M48T254V figure 16. sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 11. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data symb mm inches typ min max typ min max a 10.54 0.415 a1 8.00 8.51 0.315 .0335 a2 7.24 8.00 0.285 0.315 a3 0.38 0.015 b 0.46 0.56 0.018 0.022 d 21.21 21.84 0.835 0.860 e 17.27 18.03 0.680 .0710 ea 15.55 15.95 0.612 0.628 eb 3.20 3.61 0.126 0.142 l 2.03 2.29 0.080 0.090 shtk-a a1 a d e ea eb a2 b l a3
M48T254V 24/26 part numbering table 12. ordering information scheme note: 1. the soic packages (so28/so44) require the battery/crystal package (snaphat) which is ordered separately under the part n um- ber ?m4t32-br12sh? in plastic tube or ?m4t32-br12shtr? in tape and reel form. 2. where ?z? is the symbol for bga packages and ?a? denotes 1.27mm ball pitch for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 13. snaphat battery table example: m48t 254v ?10 za 1 device type m48t supply voltage and write protect voltage 254v = v cc = 3.0 to 3.6v; v pfd = 2.8 to 2.97v speed ?10 = 100ns package (1) za = 42.5mm x 42.5mm (2) , 1.27mm ball pitch, bga module temperature range 1 = 0 to 70c part number description package m4t32-br12sh lithium battery (120mah) snaphat sh
25/26 M48T254V revision history table 14. document revision history date rev. # revision details september 2002 1.0 first issue 31-mar-03 1.1 updated test condition (table 9 ) 19-may-03 2.0 v2.2 template update; modify package dimensions (table 10 ) 24-nov-04 3.0 product promoted to maturation code 50 (not for new design - nnd)
M48T254V 26/26 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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